Ing. Zdenek POHL, Ph.D

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Department of Signal Processing, UTIA, CAS
Pod Vodarenskou vezi 4
182 08 Praha 8
Czech Republic

phone: +420/266 052 212
fax: +420/266 052 511
email:

Current position: Senior researcher
Research interests: Informatics and programmable logic; parallel and extremely fast system-identification algorithms; FPGA implementations
Current projects: SILENSEPANACHETHINGS2DOTD03000195
Past projects: ALMARVIEMC2SURF, SCALOPES, AETHER, CAK 2, RIPAC, RECONF 2, HSLA, CAK

Qualification:
2008 Ph.D. in control engineering from the Faculty of Electrical Engineering, CTU in Prague
since 2001 member of the Signal Processing group
2001 graduated from FEE CTU Prague
Selected publications:

Pohl Z., Schier J., Licko M., Hermanek A., Tichy M.: Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping.
In: Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003. (Werner B. ed.). IEEE Computer Society Press, Los Alamitos 2003, pp. 1-6

Danek M., Pohl Z., Nasi K., Karoubalis T.: Figaro - an automatic tool flow for designs with dynamic reconfiguration.
In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005. (Rissa T., Wilton S., Leong P. eds.). Academy of Finland, Tampere 2005, pp. 590-593.

Pohl Z., Kadlec J., Sucha P., Hanzalek Z.: Performance tuning of iterative algorithms in signal processing.
In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005. (Rissa T., Wilton S., Leong P. eds.). Academy of Finland, Tampere 2005, pp. 699-702.


Other links:

All publications (UTIA library)

AS CR library