Fault Injection into Emulated ASIC Netlists Using Partial Runtime Reconfiguration of FPGA


This package contains the ExtractFL tool. This tool is part of a design flow for emulation of faults in ASIC netlists using FPGAs that was developed within the RETAC project. Faults are injected into the emulated netlist using partial runtime reconfiguration. The ExtractFl tool extracts FPGA configuration data for every considered fault from placed and routed netlists for FPGA.

Package Summary

Title ExtractFL tool
Filename extractfl.zip
License Freeware
Package content ZIP archive with the ExtractFL tool and an example
Size 3 689 734 Bytes
MD5 checksum bb316cb10d684d3e221716b6f055ad2a
Required tools
& platform
The ExtractFL tool is an executable file for Windows. No additional tools are required.

Result Category

Project number Contract section Year RIV category Comment
1QS108040510 2.3 4 S Authorized SW

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Contact Person

Please, don't hesitate to contact Jiri Kadlec to obtain more information.