The project aims at creating a new technology for diagnosing SoC-type digital circuits; project outputs will be a prototype and methodology. The method used for testing SoC circuits will be based on the so-called RESPIN architecture (IEEE P1500 compliant). The RESPIN architecture considers reconfiguration of each circuit core so that each core can be tested by the cores in its neighbourhood. Test vectors can be applied in a compressed form and the decompression can be done in the circuit using the neighbouring reconfigurable cores. The compressed test vectors for this architecture will be generated using the COMPAS tool designed and implemented by the applicant's team. The prototype will be implemented using the FPGA circuits from Xilinx. To improve the testability of the designed circuits a tool will be created that will speed up fault simulation using circuit models implemented in dynamically reconfigurable FPGA circuits.

Name: Technology for improving the testability of modern digital circuits
Provider: Academy of Sciences of the Czech Republic
Project No.: 1QS108040510
Consortium: Faculty of Mechatronics, TU Liberec
Institute of Information Theory and Automation of the AS CR
Duration: 1.1.2005 - 31.12.2008

Project presentations

Project has been presented during
  • 16th IFAC World Congress in Prague, July 4 - 8,2005, at UTIA & IDEALIST booth. (project presentation)
  • 3rd Annual ARTEMIS Conference in Graz, 23-24 May 2006, at UTIA booth
  • IST2006 event in Helsinki, 21-23 November 2006, at the PicoNet stand
  • FPL2008 conference in Heidelberg, October 8-10, at UTIA booth

Project results