SW Defined Floating Point 8xSIMD EdkDSP IP Serving for Adaptive Noise Cancellation
This application note and evaluation package describes design of reprogrammable 8xSIMD EdkDSP IP core for the 28nm FDSOI digital designs of the THINGS2DO project. The IP has been designed with support of high level flow and tested on the Zynq all programmable 28nm chip with two Arm A9 processors and programmable logic area. The developed SW API, algorithmic implementation and mapping to the 8xSIMD EdkDSP IP forms a base for the possible subsequent implementations in the 28nm FDSOI technology.
The 8xSIMD EdkDSP IP Core
The 8xSIMD EdkDSP IP Core is configured for accelerated floating point computation of the recursive FIR filter with constant parameters and for acceleration of the adaptive recursive LMS filter with unknown coefficients.. The FIR filter models the environment and generates the sequence of data measurements. The LMS filter serves for reconstruction of the unknown speaker voice with partially cancelled disturbance from the far distance source.
The 8xSIMD EdkDSP IP Core is programmed, evaluated and debugged in HW Xilinx Zynq module TE0720-IF. The 28nm Xilinx Zynq device xc7z020-2I has two 32 bit ARM Cortex A9 processors operating at 766 MHz and single MicroBlaze 32 bit soft core processor operating at 100 MHz.
|Title||SW Defined Floating Point 8xSIMD EdkDSP IP Serving for Adaptive Noise Cancellation|
|License||things2do_t20i2m4_2017_1_te0701_06.pdf for licensing conditions.|
|Package content||ZIP archive with precompiled Vivado 2017.1 projects demonstrating SW defined floating point 8xSIMD EdkDSP IP serving for adaptive noise cancellation.|
|Size||ZIP file: 349757297 Bytes
PDF file: 4386377 Bytes
|Xilinx SDK 2017.1|
|Installation notes||See things2do_t20i2m4_2017_1_te0701_06.pdf|
|Project number||Year||RIV category||Comment|
|7H14007||2018||Gfunk||Functional sample (demo)|