Tool for Preparation of Emulation of Time-Annotated ASIC Netlists


This package contains the SDFAn tool. This tool is part of the design flow for emulation of time-annotated ASIC netlists using FPGA that was developed within the RETAC project. The tool processes a circuit netlist and SDF file and creates a modified netlist that is used for emulation in an FPGA.

Package Summary

Title Tool for Preparation of Emulation of Time-annotated ASIC Netlists
License Freeware
Package content ZIP archive with the SDFAn tool and an example
Size 1 617 040 Bytes
MD5 checksum 68d6d99195266c2798a516b81afb4312
Required tools
& platform
The SDFAn tool is an executable file for Windows. No additional tools are required.

Result Category

Project number Contract section Year RIV category Comment
1QS108040510 2.3 4 S Authorized SW

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Contact Person

Please, don't hesitate to contact Jiri Kadlec to obtain more information.