Zynq Platform with UTIA EdkDSP Accelerator and Toshiba Sensor Video Processing in HW for TE0720-03-2IF SoM on TE0701-05 Carrier

Key features

This application note describes HW platform performing integration of the runtime reprogrammable EdkDSP floating point accelerator with edge detection and motion detection video processing for Toshiba Full HD colour video sensor with fixed resolution (1920x1080p60).

  • The Xilinx Zynq device xc7z020-2I has two Arm Cortex A9 processors (operating at 666 MHz), memory controller with two levels of caches and also with high performance DDR3 memory access ports. It provides also the programmable logic area used for:
    • UTIA EdkDSP (8xSIMD) floating point processor (operating at 120 MHz) connected to Xilinx MicroBlaze 32bit processor (operating at 100 MHz).
    • Input chain of video processing IPs is connecting Full HD Toshiba video sensor to input video frame buffers. The input video DMA (VDMA) controller is operating at 150 MHz.
    • Area reserved for HLS HW accelerators and data movers defined in Xilinx SDSoC 2015.4 environment. These accelerators can be controlled from Arm Cortex A9 C programs compiled in SDK 2015.4 C projects. These HLS accelerators are operating at 150 MHz.
    • Chain of output video processing IPs is connecting output frame buffers to the Full HD display connected by HDMI cable. The output VDMA controller is operating at 150 MHz.
  • UTIA EdkDSP is 8xSIMD floating point accelerator reprogrammable in runtime by change of firmware of build in PicoBlaze6 8bit controller. This is serving as a scheduler of vector operations performed in the EdkDSP is 8xSIMD floating point processor data paths. This scheduler is programmed by simple C programs compiled by simple C compiler and assembler, respecting the minimal resources of the PicoBlaze6 controller.
  • UTIA EdkDSP is 8xSIMD floating point accelerator is controlled by the 32bit MicroBlaze processor. The MicroBlaze processor is executing C programs from the DDR3 memory. It executes complex C algorithms. Algorithms can benefit from execution of selected operations effectively on the EdkDSP coprocessor connected to the MicroBlaze by local dual ported memories. MicroBlaze C programs can take benefit of overlap of data communication from DDR3 to the EdkDSP dual-ported memories with parallel computations in the EdkDSP accelerator.
  • Platform includes also the video processing chain of IPs controlled by Arm Cortex A9 processor.
  • Arm Cortex A9 processor of Xilinx Zynq is performing initialisation and synchronisation of the video processing chain. Program and the FPGA image is downloaded to the board from the Xilinx SDK 2015.4 via USB JTAG to the 1GB DDR3 located on the Zynq system on module. System can be also started directly from the SD card. Arm processor initiates the IP cores in the programmable logic (PL) part of the Zynq. It also initiates the Toshiba video sensor and the video output to the Full HD monitor with fixed 1920x1080p60 resolution and standard Full HD pixel clock 148.5 MHz.

This application note documents how designs debugged and developed in the high level SDSoC 2015.4 environment can be exported to the end-user in form of SDK 2015.4 projects.

Enclosed SDK 2015.4 projects provide space for the end-user to make some SW adaptations and customisations of the final application without the need to disclose to the end-user complete low level details about used IP cores Vivado 2015.4 project and the SDK 2015.4 board support package.

See sections 5 of this application note for specification of deliverables and license details.

Package Summary

Title Zynq Platform with UTIA EdkDSP Accelerator and Toshiba Sensor Video Processing in HW for TE0720-03-2IF SoM on TE0701-05 Carrier
Filename t20i2tm1_V54_IMPORT.zip
t20i2tm1_2015_4_te0720.pdf
License t20i2tm1_2015_4_te0720.pdf for licensing conditions.
Package content ZIP archive with precompiled Vivado 2015.4 projects demonstrating Zynq Platform with UTIA EdkDSP Accelerator and Toshiba Sensor Video Processing in HW for TE0720-03-2IF SoM on TE0701-05 Carrier.
Size ZIP file: 19392614 Bytes
PDF file: 3154539 Bytes
Required tools
& platform
Xilinx SDK 2015.4
Installation notes See t20i2tm1_2015_4_te0720.pdf

Result Category

Project number RIV category Comment
7H14007 Gfunk Functional sample (demo)

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Contact Person

Please, don't hesitate to contact Jiri Kadlec to obtain more information.