Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-30-1 SoM on EMC2-DP-V2 Carrier
This application note describes demos of HW accelerated Full HD HDMI video processing and HW accelerated floating point filters computed in (8xSIMD) EdkDSP accelerators on the largest Zynq platform with the Kintex PL fabric supported by the free Xilinx Vivado 2015.4 and SDK 2015.4 tool chain:
- 3 edge detection video processing designs (sh01, sh02, sh03)
- These demos document the possibility to define different HW paths by different source C/C++ functions. This is important for covering of the borders lines of the parallel processed parts of the frame.
- HW accelerators can be programmed for the number of processed micro-lines.
- These demos enable efficient, synchronised parallel execution of accelerated data paths and ARM Cortex A9 standalone C code.
- 1 motion detection video processing design (md01)
- This demonstrates the pipelined parallel execution of HW video processing accelerators.
- HW accelerators work with fixed number of processed micro-lines (1080 micro-lines) in this case.
The evaluation version of the package can be downloaded from UTIA www pages free of charge.
The evaluation package includes evaluation bitstreams with three (8xSIMD) EdkDSP accelerators working in parallel with the HW-accelerated edge detection and motion detection algorithms for the Full HD HDMII-HDMIO video processing on the Trenz TE0715-03-30-1I module located on the Sundance EMC2-DP-V2 carrier with the FMC card.
|Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-30-1 SoM on EMC2-DP-V2 Carrier
|s30i1hm4_2015_4.pdf for licensing conditions.
|ZIP archive with precompiled Vivado 2015.4 projects demonstrating Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-30-1 SoM on EMC2-DP-V2 Carrier.
|ZIP file: 78393555 Bytes
PDF file: 4832568 Bytes
|Xilinx SDK 2015.4
|See application note
|Functional sample (demo)