Dynamic Programmable Logic Reconfiguration for Zynq


The architecture of the Zynq all programmable SoC from Xilinx consists of Dual ARM Cortex-A9 cores with NEON DSP/FPU engine and of programmable logic (PL). This demo shows how the PL can be fully reconfigured without using partial dynamic reconfiguration. This way, at the cost of the longer time needed for reconfiguration of PL we can cover 90% typical applications using dynamic reconfiguration where CPU cores are running while PL adapts.

The dynamic reconfiguration demo consists from two bitstreams for PL configuration and one pre-compiled software code. The software application demonstrates the PL reconfiguration. It also allows to control reset and clocks for PL. The precompiled demo prepared for ZC702 SD card can be found in boot_image/sd_card.

Package Summary

Title Dynamic Programmable Logic Reconfiguration for Zynq
Filename plreconf.zip
Size ZIP file: 983033 Bytes

Result Category

Project number Year RIV category Comment
7H14005 2015 Gfunk Functional sample (demo)

Contact Person

Please, do not hesitate to contact Zdenek Pohl to obtain more information.