Adaptive RLS Algorithms Reference Implementations for 32 bit Win7

Description

This application note aims to present set of adaptive recursive least squares system identification algorithms based on the Bayesian extensions of real-time adaptive system identification as well as extending the existing recursive least square adaptive algorithms for estimation of time varying parameters in the applications of acoustic signal processing. The included reference adaptive algorithms are implemented in Matlab 2015b (32bit). Algorithms serve as "golden" reference models for the embedded implementations on dedicated processors like Arm Cortex A9 and the FPGA programmable logic accelerators in devices the Xilinx Zynq. Algorithms are numerically robust. Algorithms are implemented in double precision floating point (64bit), single precision floating point (32bit) and in logarithmic arithmetic with precision 32bit and 19bit. All algorithms except for lattice filter are implemented both with exponential forgetting and directional forgetting, which use more complex computation and allows to "forget" previous information only if incoming data are bringing new information with them. In several cases identification process can benefit from this, as it will be shown on examples in the following chapters. Lattice filter, however, is performed with exponential forgetting only.

The application note also presents adaptive recursive least squares system identification algorithms taking advantage of dynamic normalization of the core of the algorithm into the guarantied range ˂-1, 1˃ for all variables. These algorithmic cores are suitable for the fixed-point implementation (14bit). Naturally, the fixed-point implementation with representation of all variables as only 14bit fixed-point numbers results in decreasing precision. But it opens possibility of potentially ultralow power implementation of recursive RLS on parallel HW accelerators with custom fixed point arithmetic. This is crucial for implementing in low power embedded systems. As a result then using these algorithms in fixed-point we plan to develop and implement systolic, pipelined SoC IP core in form of HW accelerator in the programmable logic part of the Xilinx Zynq device (28nm) and possibly also in the 16nm Zynq UltraScale+ device.

Evaluation license

The evaluation version of the package can be downloaded from UTIA www pages free of charge.

The evaluation package includes .m scripts with DSP algorithms pre-compiled as .mexw32 files for MATLAB R2015.b and two standalone applications for Win7/Win10 32/64bit (for users without MATLAB).

Package Summary

Title Adaptive RLS Algorithms Reference Implementations for 32 bit Win7
Filename dsp_1_6_32bit.zip
dsp_1_6_32bit.pdf
License
  • Included DSP algorithms pre-compiled as .mexw32 files have no time restriction.
  • The evaluation package can be downloaded and used free of charge.
  • Source code of these DSP algorithms is not provided in this evaluation package.
Package content ZIP archive with adaptive RLS algorithms reference MATLAB R2015b (32bit) implementations and istallation packages for use without MATLAB on Win7/Win10 (32/64bit).
Size ZIP file: 4759756 Bytes
PDF file: 4612166 Bytes
Required tools
& platform
Win7/Win10 32/64bit with MATLAB R2015.b (32bit) or Win7/Win10 32/64bit without MATLAB
Installation notes See dsp_1_6_32bit.pdf

Result Category

Project number Year RIV category Comment
8A17006 2017 R Software

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Contact Person

Please, don't hesitate to contact Jiri Kadlec to obtain more information.