Accelerator for Computation ADSL Line Response

Description

Accelerator computes simulation of response of ADSL line including several separated communication lines. Each communication line influences all the rest communication lines and this fact is used for computation of response whole ADSL line. The accelerator is based on the FPGA technology (Altera Stratix II). Appropriate communication function for Matlab have been implemented.

Package Summary

Title ADSL Line Response Accelerator
Filename ADSLdemo.zip
License Freeware
(See the 'license.txt' file in the package.)
Package content ZIP archive with accelerator (bitstream) and communication functions for Matlab
Size 1700035 Bytes
MD5 checksum f1047e8ce37c27be83aca9bdab14fa40
Required tools
& platform
Matlab R14 or newer for Windows (OS dependent), Quartus II
Development board "Stratix II EP2S180 DSP Development Board"
Installation notes See the 'readme.txt' file in the package.

Result Category

Project number Contract section Year RIV category Comment
1ET300750402 2.4 2-3 S Functional sample (demo)

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Contact Person

Please, don't hesitate to contact Zdenek Pohl to obtain more information.