EdkDSP Accelerator IP Evaluation in Vivado 2014.4 Artix7 AC701 board

Description

This application note describes precompiled Vivado 2014.4 Artix7 designs with the floating point EdkDSP accelerators and examples. The evaluation MicroBlaze SoC design with the AXI-lite bus is based on the Xilinx BIST (build in self-test) provided by Xilinx for the Artix7 AC701 board and the Vivado 2014.4 design flow. The network HW controller is supporting 1Gbit/100Mbit/10Mbit standards with HW DMA and a SW stack based on the lwIP TCP/IP stack library v1.4.1 with Xilinx adapter v2.2. The implementation follows guidelines described in the Xilinx application note XAPP1026. The MicroBlaze processor is controlling 5 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable computing data path, controlled by a PicoBlaze6 controller. This evaluation package is provided by UTIA for the Xilinx AC701 board with the 28nm Artix7 xc7a200t-2 device. This application note explains how to install and use the demonstrator on Windows7, (32 or 64 bit) and the Xilinx AC701 development board.

These key features are demonstrated:

  • WWW server running on Artix7 AC701 board with the lwip141 stack running in RAW mode on "bare metal" with standalone bsp or SOCKET mode with the Xilkernel bsp, supporting the POSIX compatible threads
  • TFTP server running on Artix7 AC701 board with the lwIP stack running in RAW mode or SOCKET mode.
  • RAM based file system with file system present in the DDR3 memory on the AC701 board.
  • 5 reprogrammable floating point accelerators for local embedded computing on the Artix7 28nm chip.
  • Demo implementation of an adaptive acoustic noise cancellation on 1 of the 5 EdkDSP accelerators is computing the recursive adaptive LMS algorithm for identification of regression filter with 2000 coefficients in single precision floating point arithmetic with this sustained performance:
    • 754,0 MFLOP/s on a single 125 MHz (8xSIMD) EdkDSP accelerator (only 1 of 5 units is used).
    • 8,6 MFLOP/s on the 100 MHz MicroBlaze processor with the floating point HW unit.
  • The EdkDSP accelerators can be reprogrammed by firmware. Programming of firmware is possible in C with the use of the UTIA EDKDSP C compiler. Each accelerator can store two firmware programs simultaneously. Each accelerator can swap firmware programs in only few clock cycles in the runtime.
  • This evaluation package supports download of alternative firmware to EdkDSP accelerators from internet in parallel with the execution of the current firmware. This is demonstrated by the download of firmware by the TFTP server and by swap of the firmware (computing the acoustic room-response by FIR filter) to firmware performing the adaptive LMS identification of filter coefficients in the adaptive acoustic noise cancellation demo.
  • The EdkDSP accelerator is providing single-precision floating point results bit-exact identical to the reference software implementations running on the MicroBlaze with the Xilinx HW single precision floating point unit.
  • Single 125 MHz (8xSIMD) EdkDSP accelerator is 87x faster than computation on the performance optimized 100 MHz MicroBlaze with HW floating point unit, in the presented case of the 2000 tap adaptive LMS filter.
  • The floating point 2000 tap coefficients FIR filter (acoustics room model) is computed by single 125 MHz (8xSIMD) EdkDSP accelerator with the floating point performance of 1111 MFLOP/s. Peak performance (only theoretical) of each 125 MHz (8xSIMD) EdkDSP accelerator is 2 GFLOP/s.
  • Peak performance of the five instances of 125 MHz (8xSIMD) EdkDSP accelerators implemented in this demo design is 10 GFLOP/s (this is only theoretical peak figure).
  • This evaluation package presents (8xSIMD) EdkDSP accelerator family with a single pipelined floating point divider data path. The IP cores differ by supported vector floating point operations, area used on the device and by power consumption.
  • Precompiled evaluation designs also support debug of one EdkDSP IP core accelerator in the Vivado 2014.4 Hardware Manager in real-time. This is possible due to the support of the in-circuit logic analyser (ILA).

What is included

The evaluation package includes precompiled Vivado 2014.4 Artix7 designs with floating point EdkDSP accelerators and examples in form of Xilinx SDK 2014.4 SW projects for Windows 7 (32 or 64 bit):

  • 8 evaluation versions of precompiled Artix7 designs. Each design contains one MicroBlaze and five instances of the EdkDSP accelerators. Each accelerator has 8xSIMD floating point data paths and programmable PicoBlaze6 controller for scheduling of floating point vector operations in the accelerator. The MicroBlaze works with 100 MHz system clock and EdkDSP acelerators use 125 MHz clock. The MicroBlaze processor works with 1Gb Ethernet with DMA controller and 1GB DDR3 memory. Designs are compiled in Xilinx Vivado 2014.4.
  • UTIA is providing source code for the demo applications and SW projects for the Xilinx SDK 2014.4. These source code projects are compiled with the UTIA library libwal.a serving for the EdkDSP communication and the library libmfsimage.a with the initial file system supporting the simple www server GUI example.
  • The included evaluation designs with UTIA EdkDSP accelerators have HW limitation of maximal number of performed accelerated vector operations.
  • The UTIA EDKDSPC C compiler is provided in form of 4 binary applications running in the Ubuntu OS installed in the VMware Workstation 12 Player.
  • The firmware for accelerators is provided in source code and also in format of binary file headers to enable initial evaluation of the EdkDSP accelerator IP cores without the need to install the EDKDSPCC C compiler.
  • UTIA partners of the Eniac THINGS2DO project, can get from UTIA the release version of Vivado 2014.4 HW design projects with the evaluation versions of the EdkDSP IP core accelerators (in the Vivado 2014.4 IP netlist format) for free. See chapter 6 of this application note for specification of deliverables for the Eniac THINGS2DO project partners with the license details.
  • Release versions of Vivado 2014.4 HW design projects and release version of EdkDSP IP core accelerators for the Xilinx AC701 board is offered by UTIA. All customers can order and buy from UTIA the release version of this demo. It includes the Vivado 2014.4 HW design projects with the EdkDSP accelerators (in the Vivado 2014.4 IP netlist format) with the HW limitation of maximal number of performed vector operations removed. See sections 7 of this application note for specification of deliverables and license details.

Package Summary

Title EdkDSP Accelerator IP Evaluation in Vivado 2014.4 Artix7 AC701 board
Filename d_44.zip
Utia_EdkDSP_Vivado_2014_4_AC701.pdf
License Utia_EdkDSP_Vivado_2014_4_AC701.pdf for licensing conditions.
Package content ZIP archive with precompiled Vivado 2014.4 projects demonstrating Utia_EdkDSP HW Floating-point accelerators and source code of SDK 2014.4 software projects with Utia_EdkDSP libraries.
Size ZIP file: 79020488 Bytes
PDF file: 3865959 Bytes
Required tools
& platform
Xilinx Vivado 2014.4, Xilinx SDK 2014.4, Xilinx AC701 development board
Installation notes See Utia_EdkDSP_Vivado_2014_4_AC701.pdf

Result Category

Project number RIV category Comment
7H14007 Gfunk Functional sample (demo)

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Please, don't hesitate to contact Jiri Kadlec to obtain more information.