UTIA EdkDSP Platform Demonstrator on Xilinx SP605 Board PLB Bus

Key features

This application note describes the EdkDSP platform demonstrator package provided by UTIA for the Xilinx SP605 designs with PLB bus. It explains how to install and use the demonstrator on Windows7, (32 or 64 bit).

  • Implementation of adaptive acoustic noise cancellation: Demonstrated accelerators compute the recursive adaptive LMS algorithm for regression filter with 2000 coefficients with the sampling frequency 80 KHz in single precision floating point arithmetic. This corresponds to the sustained performance of 580 MFLOP/s.
  • The accelerators can be reprogrammed by the firmware. The programming is possible in C with the use of the UTIA EDKDSP C compiler. Accelerators can be programmed with two firmware programs. Designs can swap in the real time the firmware in only few clock cycles in the runtime.
  • The alternative firmware can be downloaded to the EdkDSP accelerators in parallel with the execution of the current firmware. This is demonstrated by swap of the firmware for the FIR filter room response to the firmware for adaptive LMS identification of the filter coefficients in the acoustic noise cancellation demo.
  • The EdkDSP accelerator is providing bit-exact identical single-precision floating point results as the reference software implementation running on MicroBlaze with the Xilinx HW single precision floating point unit.
  • The EdkDSP accelerator is 140x - 160x faster than computation on area optimized 83,3 MHz MicroBlaze with HW floating point unit, in presented case of the 2000 tap adaptive LMS filter.
  • The floating point 2000 tap coefficients FIR filter (acoustics room model) is computed with the floating point performance 820 MFLOP/s. The peak performance (only theoretical) is 1.5 GFLOP/s.
  • The EdkDSP accelerators are internally organised with 8xSIMD data paths.
  • This evaluation package presents 2 EdkDSP accelerator families: one family without pipelined floating point divider data path and one family with a single pipelined floating point divider data path. The members of both families differ by size and by supported vector floating point operations.
  • The floating point applications can be scheduled inside of the EdkDSP accelerator by the Xilinx PicoBlaze6 processor. Each firmware program has maximal size of 4096 (18 bit wide words).
  • All designs include Xilinx display controller 1280x792p60 for digital DVI or analogue RGB 24 bit display.

What is included

This EdkDSP platform evaluation package includes these deliverables for the Windows 7 (32 or 64bit):

  • 8 evaluation versions of EdkDSP accelerators with 8xSIMD floating point data paths integrated in 8 precompiled designs (MicroBlaze 83,3 MHz, Accelerator 95,2 MHz) and in 8 precompiled designs (MicroBlaze 83,3 MHz, Accelerator 83,3 MHz) with PLB bus. Designs are compiled in Xilinx XPS 14.5.
  • All 16 precompiled designs include the Xilinx PLB bus video controller and an evaluation version of the Xilinx xps_Soft_TMAC 1Gb Ethernet controller with SDMA data path to the external DDR3 memory.
  • SW demos are using the Xilinx Xilkernel OS, LwIP package and the memory file system xilmfs.
  • UTIA is providing source code for the demo applications and SW projects for the Xilinx SDK 14.5. These source code projects are compiled with the UTIA libraries libwal.a, libjpg.a, librgb.a and libmfsimage.a.
  • The evaluation versions of the UTIA EdkDSP accelerators compiled in the designs and the Xilinx TEMAC 1Gb Ethernet controller compiled in the designs run only for a limited time. The time limit for the Xilinx TEMAC is several hours. Evaluation versions of the UTIA EdkDSP accelerators is related to maximal number of performed vector operations.
  • The UTIA EdkDSPC C compiler is provided as 3 executable applications for Ubuntu in the VMware Player.
  • The firmware is also provided in precompiled files to enable testing of accelerators without C compiler.
  • A release version of the EdkDSP package for SP605, PLB bus is offered by UTIA. It provides EdkDSP accelerators for the SP605 in form of PLB netlist pcores with main limitations of the free evaluation package removed. See sections 4-6 of the application note for specification of deliverables and license details.

Package Summary

Title UTIA EdkDSP Evaluation version SP605, PLB
Filename d_145_6s_plb_ini.zip
License See Utia_EdkDSP_145_SP605.pdf for licensing conditions.
Package content ZIP archive with precompiled ISE 14.5 HW projects demonstrating Utia_EdkDSP HW Floating-point accelerators and source code of SDK 14.5 software projects with Utia_EdkDSP libraries.
Size ZIP file: 43322287 Bytes
PDF file: 3072121 Bytes
Required tools
& platform
Xilinx ISE 14.5, Xilinx SDK 14.5, Xilinx SP605 Evaluation board
Installation notes See Utia_EdkDSP_145_SP605.pdf

Result Category

Project number Year RIV category Comment
7H12004 2014 Gfunk Functional sample (demo)

Contact Person

Please, do not hesitate to contact Jiri Kadlec to obtain more information.