UTIA EdkDSP Demonstrator in Xilinx 3S700AN FPGA with Embedded FLASH and NV RAM

Key features

This application note describes designs for Xilinx Spartan3AN FPGA 3S700AN with serial configuration FLASH embedded in the FPGA chip. The note describes use of an UTIA EdkDSP demonstrator package. The document explains how to install and use the demonstrator on Windows7, (32 or 64 bit). Package can be also installed and used without modification on x86 PC with Linux OS or Windows XP (32 or 64 bit).

What is included

This 3S700AN evaluation package includes:

  • 12 evaluation versions of designs for the starter Kit 3S700AN. All designs include one EdkDSP accelerator with single reconfigurable floating point data path. MicroBlaze works with 50 MHz clock, EdkDSP accelerator and XGA display controller works with 75 MHz clock, DDR2 works with 100 MHz clocks.
  • Designs have been developed in the Xilinx XPS 14.5 tool chain.
  • All designs include the Xilinx xps_ethernet_lite 10/100Mb Ethernet controller.
  • All 12 precompiled designs include XGA RGB565 1024x768p70 video controller based on the direct access to the external DDR2 memory by the native port interface (NPI) of the Xilinx multi-port memory controller (MPMC).
  • Larger SW demos are using the Xilinx Xilkernel OS, the LwIP package and the Xilinx memory file system package xilmfs.
  • UTIA is providing source code for the demo applications and SW projects for the Xilinx SDK 14.5. These source code projects are linked with UTIA libraries libwal.a, libjpg.a, librgb.a and libmfsimage.a.
  • The UTIA EdkDSPC C compiler is provided in form of executable binary applications for an Ubuntu Linux 32bit executable in Windows 7 (32 or 64 bit). Ubuntu can run in VMware Player in Windows 7.
  • The user part of the demonstration firmware is provided in source C code and it is also provided as precompiled binary files to enable the initial evaluation of the EdkDSP reconfigurable accelerators without installation of the UTIA EdkDSPC C compiler.

Demonstrator packages:

  • The evaluation versions of the UTIA EdkDSP accelerators compiled in the designs have HW limit of maximal number of performed vector operations after each power-off of the 3S700AN device. See sections 4-6 of this application note for specification of deliverables for PANACHE project partners and the license details.
  • A free evaluation version of the EdkDSP package for Spartan SK 3AN700, PLB bus is offered by UTIA to the PANACHE project partners for zero cost. It provides the Xilinx XPS projects for Spartan SK 3AN700, with the evaluation versions of EdkDSP accelerators for the Spartan SK 3AN700 in form of netlisted PLB pcores. See sections 4-6 of this application note for specification of deliverables for PANACHE project partners and the license details.
  • A release version of the EdkDSP package for Spartan SK 3AN700, PLB bus is also offered by UTIA commercially. It provides EdkDSP accelerators for the Spartan SK 3AN700 in form of netlisted PLB pcores with the main HW limitation of the free evaluation packages removed. See sections 4-6 of this application note for specification of deliverables and license details.
  • A release version of the EdkDSP package for Spartan SK 3AN700, PLB bus is also offered by UTIA commercially. It provides EdkDSP accelerators for the Spartan SK 3AN700 in form of netlisted PLB pcores with the main HW limitation of the free evaluation packages removed. See sections 4-6 of this application note for specification of deliverables and license details.

Package Summary

Title UTIA EdkDSP Demonstrator in Xilinx 3S700AN FPGA with Embedded FLASH and NV RAM
Filename d_145_3an_plb.zip
Utia_EdkDSP_145_S3AN.pdf
License Utia_EdkDSP_145_S3AN.pdf for licensing conditions.
Package content ZIP archive with precompiled ISE 14.5 projects demonstrating Xilinx Spartan3AN FPGA 3S700AN with serial configuration FLASH embedded in the FPGA chip with Utia_EdkDSP HW Floating-point accelerators and source code of SDK 14.5 software projects.
Size ZIP file: 21193082 Bytes
PDF file: 2249347 Bytes
Required tools
& platform
Xilinx ISE 14.5, Xilinx SDK 14.5, Xilinx 3S700AN Starter Kit
Installation notes See Utia_EdkDSP_145_S3AN.pdf

Result Category

Project number RIV category Comment
7H14006 Gfunk Functional sample (demo)

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Contact Person

Please, don't hesitate to contact Jiri Kadlec to obtain more information.