Compact Zynq System 2017.4 with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator

Supported Trenz Electronic Modules:
TE0720-03-2IF, TE0720-03-1QF, TE0720-03-14S-1C
Supported Trenz Electronic Carrier Boards:
TE0703-05, TE0706-02


This report describes design of compact HW system based on Zynq all programmable 28nm chip with one or two Arm A9 processors and programmable logic area. System is optimised for Ethernet connected computing nodes serving for industrial automation, local data processing and data communication. The documented HW architecture is one of candidates for wider use within the ECSEL Productive 4.0 project for the edge computing node in the Industry 4.0 solutions. Two carrier boards and three Zynq modules from Trenz Electronic are supported.

SD cards files with demo examples can be downloaded here:

The demonstrated Zynq systems include the run-time reprogrammable 8xSIMD EdkDSP IP core. It combines the MicroBlaze and the floating point single instruction multiple data (SIMD) data flow unit (DFU). The SIMD DFU is controlled by a run-time reprogrammable finite state machine implemented by Xilinx PicoBlaze6 8 bit controller with dedicated embedded (on Zynq executed) C compiler.

The application note describes the installation of the HW system, the SW API, algorithmic implementation and mapping to the 8xSIMD EdkDSP IP. Presented HW system is also compatible with the Xilinx SDSoC 2017.4.1 design environment. The SDSoC is supporting automated compilation of user-defined C/C++ ARM functions into HW accelerators with several types of data movers (zero-copy, DMA, SG-DMA) and the automated integration of generated accelerators as an ARM Linux operating system or standalone application.

Package Summary

Title Compact Zynq System 2017.4 with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator
License productive40_TE0720-2IF-1QF-14S_TE0703-05_TE0706-02_2017-4-1_2018_05_15.pdf for licensing conditions.
Package content ZIP archive with precompiled Vivado 2017.4 projects demonstrating Compact Zynq System 2017.4 with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator.
Size ZIP file: 43301108 Bytes
PDF file: 5141977 Bytes
Required tools
& platform
Xilinx SDK 2017.4
Installation notes See productive40_TE0720-2IF-1QF-14S_TE0703-05_TE0706-02_2017-4-1_2018_05_15.pdf

Result Category

Project number Year RIV category Comment
ECSEL 737459 2018 Gfunk Functional sample (demo)

Contact Person

Please, do not hesitate to contact Jiri Kadlec to obtain more information.