Smart Multicore Embedded SYstems

SMECY is an ARTEMIS project number 100230. The project is running from February 1, 2010 until January 31, 2013.

SMECY envisions that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments which, due to improved performance, energy and cost properties, will extensively penetrate the embedded system industry in a few years. This will affect and shape the whole business landscape, e.g. semiconductor vendors need to be capable of offering advanced multi-core platforms to diverse application sectors, IP providers need to re-target existing and develop new solutions to be compatible with evolving multi-core platforms and the need of embedded system houses, in addition to product architecture adaptations and renewing their system, architecture, software and hardware development processes. The mission of SMECY is to develop new programming technologies enabling the exploitation of many (100s) core architectures. The goal of this ARTEMIS project is to launch an ambitious European initiative to match initiatives in Asia (e.g. teams funded by JST/CREST programmes) and USA (e.g. PARLAB in Berkeley, Parallel@illinois and Pervasive Parallelism Laboratory in Stanford) and to enable Europe to become the leader.

The vision of the SMECY consortium is that a holistic approach for the integration of multi-core SoC and embedded software technologies is required. Then, the mission of the project is to develop programming and design methods, multi-core architectural solutions and associated supporting tools enabling the exploitation of many (100s) core architectures.
Multi-core technologies are strategic for industry in all areas of embedded systems. One of the grand challenges with multi-core technology is to develop efficient design and development tools for multi-core architectures for various resource-constrained embedded system applications belonging to the ARTEMIS focus: consumer electronics,wireless communication and transportation systems.
The joint goals of SMECY are to develop new programmable architectural solutions based on multi-core technology, and associated supporting tools in order to master complete system design of future smart multi-core embedded systems. All of this is strongly driven by the requirements and constraints from different application areas as well as the target platform. To be efficient the front-end / back-end take both the application requirements and the platform constraints into account.
The hardware platforms and the development tools developed in the project will be demonstrated and evaluated for a certain set of representative applications provided by industrial partners of SMECY, such as radar systems, video/audio treatments and energy efficient wireless communication systems.

Please, do not hesitate to contact Jiri Kadlec for more information.

Acronym: SMECY
Name: Smart Multicore Embedded Systems
Project No.: Artemis JU 100230
MSMT 7H10001
Consortium: Commissariat a l'Energie Atomique, France
ACE Associated Compiler Experts bv, Netherlands
Aristotle University of Thessaloniki, Greece
Brno University of Technology, Czech Republic
CIP plus s.r.o., Czech Republic
Danmarks Tekniske Universitet, Denmark
Free2Move AB, Sweden
Thomson Grass Valley France SA, France
Hellenic Aerospace Industry S.A., Greece
Hogskolan i Halmstad, Sweden
HPC Project, France
Nethawk Oyj, Finland
Politecnico di Milano Dipartimento di Elettronica e Informazione, Italy
Politecnico di Torino, Italy
Realtime Embedded AB, Sweden
SKYLAB Industries, France
Saab Microwave Systems, Sweden
STMicroelectronics S.r.l., Italy
STMicroelectronics (Grenoble 2) SAS, France
Tellabs Oy, Finland
Thales Research & Technology (FR), France
Thales Research & Technology (UK), United Kingdom
Technische Universiteit Delft, Netherlands
Université Joseph Fourier grenoble 1, France
Alma Mater Studiorum - Universita di Bologna, Italy
University of Ioannina, Greece
Institute of Information Theory and Automation of the AS CR, Czech Rep.
Valtion teknillinen tutkimuskeskus, Finland
Duration: February 1, 2010 - January 31, 2013