Presentations

General

European Projects Projects with Nation Funding Logarithmic Arithmetic in Today's Computing The Flow-Transfer Level Modelling: Data-Driven Circuits in the Clock-Synchronous Domain  

ALMARVI

Dense Optical Flow Demo Video Processing with Python 1300 Sensor and EdkDSP Accelerator Walnut Harvest Protection Use Case    

EMC2

Asymmetric Multiprocessing on EMC2-DP        

THINGS2DO

UTIA & IMA in Things2Do project        

IDEAS

EdkDSP reprogammable floating point accelerators on FPGA with HDMI video I/O EdkDSP reprogammable floating point accelerators on Kintex FPGA with HDMI      

SMECY

In-circuits, run-time compiler of finite state machines for the UTIA EdkDSP customizable accelerators UTIA EdkDSP Platform in the SMECY Project SMECY: Video Surveillance Application Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs  

SCALOPES

Blind image deconvolution algorithm on NVIDIA CUDA platform Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique Reconfigurable Hardware Objects for Image Processing on FPGAs Resource Manager for Heterogeneous UTIA DSP Platform  

AppleCore

Architecture Paradigms and Programming Languages for Efficient programming of multiple CORES Micro-Threaded LEON3 Processor UTLEON3 - SPARC v8 with Micro-Threading    

ÆTHER

Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC Floating-Point DSP Acceleration in FPGAs: The First Step Towards the SANE Concept Reconfigurable Handel-C FSL Accelerators for MicroBlaze Accelerating MicroBlaze FP Operations MicroBlaze Co-Processor: LS Lattice with Order Portability Estimation
PCORE Accelerators Library - GSFAP PCORE Accelerators Library - (N)LMS PCORE Accelerators Library - LS Lattice Floating Point Accelerators for MicroBlaze - Partial Runtime Reconfiguration Floating Point Accelerators for MicroBlaze EDK-Based Systems
FSL/PLB Floating Point Accelerators for Xilinx MicroBlaze (ISE/EDK 10.1 and 11.2)        

RECONF2

RECONF - Project Presentation MATLAB/Simulink Based Methodology for Rapid FPGA Prototyping FPGA Prototyping Using Extensions to MATLAB/Simulink Dynamic Reconfiguration for Atmel FPGAs Autocorrelation Demo
FPSLIC Prototyping Board ADK1 Design Guidelines for AT40K/AT94K Dynamic Reconfiguration Extended FPSLIC Platform for Dynamic Reconfiguration Automatic Partitioning for Dynamic Reconfiguration and Retiming 24-bit Floating-Point Accelerator in Atmel FPSLIC and Xilinx Virtex2
AVR Core Supported Dynamic Reconfiguration Dynamic Reconfiguration of FPGAs FPSLIC Prototyping Board for Portable Applications ADK1 FPSLIC IP CORES for ADK1 Front End Tools for a Dynamic Reconfiguration
GIN - A Note-Taker for Blind People: An Example of Using Dynamic Reconfiguration of FPGAs Dynamic Reconfiguration in FPGA-Based SoC Designs Figaro - An Automatic Tool-Flow for Designs with Dynamic Reconfiguration Design Methodology and Environment for Dynamically RECONFigurable FPGAs Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC

HSLA

Logarithmic (dual) ALU Core Logaritmická (dvojitá) aritmetická jednotka Adaptive Recursive Least Squares Lattice Filter Adaptivní Lattice filtr Lattice IP Core used in Real-time Lattice Demo on XESS Board
RLS Lattice Macros for Virtex/E/Virtex2 with LNS ALU 19/32-bit Adaptive Recursive Least Square Lattice Filter Logarithmic Dual Pipelined ALU Macros 19-bit and 32-bit Matlab Toolbox for High-Level Bit-Exact Emulation of FPGA Designs Pipelined Implementations of the a Priori Error-Feedback LSL Algorithm Using Logarithmic Arithmetic
Logarithmic Arithmetic Core Based RLS Lattice Implementation European Logarithmic Microprocessor Floating-Point Like Arithmetic for FPGA    

VLAM

Reconfiguration of FPGAs: Data Logger in Three FPGA Configurations in Celoxica RC10 Floating Point Basic Computing Elements for Xilinx MicroBlaze PLB bus in SDK 13.1 VLAM Virtual Laboratory of Microprocessor Technology Applications    

SESAp

Participation in the Evolution of the Standardization for Embedded Software for Automotive Industry Floating-Point DSP Acceleration in FPGAs: The First Step Towards the SANE Concept Reconfigurable Handel-C FSL Accelerators for MicroBlaze HW Co-simulation with communication server from MATLAB/Simulink Accelerating MicroBlaze FP Operations

Orpheus

Digital Video-Sensoric System of a Reconnaissance Robot Accelerator for Decoding Convolution and Reed-Solomon Code      

ADSL

Performance Tuning of Iterative Algorithms in Signal Processing Specification of Qualitative Criteria and Optimization of Resources for Broadband Access Networks Architecture Design for FPGA Implementation of Finite Interval CMA Accelerator for Decoding Convolution and Reed-Solomon Code  

RETAC

Reconfigurable Testing Accelerator Floating-Point DSP Acceleration in FPGAs: The First Step Towards the SANE Concept A Novel Emulation Technique that Preserves Circuit Structure and Timing Reconfigurable Emulator for Time-Annotated ASIC Netlists  

RIPAC

Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA Reconfigurable Image Processing Accelerator Simulink as a Tool for Prototyping Reconfigurable Image Processing Applications - RIPAC Simulink Model Converter for Embedded Video Accelerator Reconfigurable Image Processing Accelerator
Rapid Prototyping Platform for Reconfigurable Image Processing        

CAK2

Dynamic Reconfiguration in FPGA-Based SoC Designs Center of Applied Cybernetics Reconfiguration of FPGAs: Data Logger in Three FPGA Configurations in Celoxica RC10 Floating-Point DSP Acceleration in FPGAs: The First Step Towards the SANE Concept Reconfigurable Handel-C FSL Accelerators for MicroBlaze
GSFAP Adaptive Filtering using Log Arithmetic for Resource-Constrained Embedded Systems Accelerating MicroBlaze FP Operations MicroBlaze Co-Processor: LS Lattice with Order Portability Estimation PCORE Accelerators Library - GSFAP PCORE Accelerators Library - (N)LMS
PCORE Accelerators Library - LS Lattice Decoding Convolution and Reed-Solomon Code in FPGA Image processing for microbiology - Analysis of yeast colony growth PCORE Accelerators Library  

CAK

Alpha Accelerator for Real Time Workshop - Windows Target Intellectual Property Cores Design for Programmable Logic IP Cores Design for Programmable Logic Prototyping of DSP Algorithms on FPGA Lattice IP Core used in Real-time Lattice Demo on XESS Board
RLS Lattice Macros for Virtex/E/Virtex2 with LNS ALU 19/32-bit Matlab Toolbox for High-Level Bit-Exact Emulation of FPGA Designs Logarithmic Arithmetic Core Based RLS Lattice Implementation Floating-Point Like Arithmetic for FPGA RLS Lattice - Celoxica RC200 Demo
Using Logarithmic Arithmetic for FPGA Implementation of the Givens Rotations MATLAB/Simulink Based Methodology for Rapid FPGA Prototyping FPGA Implementation of the Adaptive Lattice Filter Prototyping of DSP Algorithms on FPGA FPGA Prototyping Using Extensions to MATLAB/Simulink
Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA Scalable, Short-Latency Floating-Point FPGA Implementation of Recursive QR Update Using LNS Arithmetic GIN - A Note-Taker for Blind People: An Example of Using Dynamic Reconfiguration of FPGAs Performance Tuning of Iterative Algorithms in Signal Processing
Architecture Design for FPGA Implementation of Finite Interval CMA        

GA-2137

FPGA Modelling for High-Performance Algorithms AVR Core Supported Dynamic Reconfiguration Figaro - An Automatic Tool-Flow for Designs with Dynamic Reconfiguration Fault Classification for Self-Checking Circuits Implemented in FPGA Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC
Floating-Point DSP Acceleration in FPGAs: The First Step Towards the SANE Concept        

GIN

GIN - A Note-Taker for Blind People: An Example of Using Dynamic Reconfiguration of FPGAs        

IST World

Knowledge Base for RTD Competencies in IST        

Cosine

Coordinating Strategies for Embedded Systems        

OKO IST

Branch Contact Organization for IST