Our group focuses on research, development and implementation of advanced digital signal processing algorithms, mainly in the fields of adaptive control and audio processing. We build on our experience with statistics, namely with the Bayesian approach to system identification and modeling, as well as the relevant fields of linear algebra.

Our target platforms are Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs). We use Matlab/Simulink to specify, model and verify algorithms that we later convert and synthesize to HW. As such specialized solutions are likely to be used in embedded systems, we also research features that result in extremely fast execution, use small amount of memory, small chip area or low power consumption. We achieve this both through designing new or modifying existing DSP algorithms, and using architectural properties such as dynamic reconfiguration of FPGAs...

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Dotazník pro řidiče k využívání vybraných asistenčních systémů

Cílem je zmapovat postoje a zkušenosti českých řidičů a řidiček s pokročilými asistenčními systémy v automobilech (ADAS). Výzkum probíhá v rámci projektu "Adaptace človĕka na asistenční systémy pro řidiče v motorových vozidlech" (TA ČR, program OMEGA). Vyplnĕní dotazníku zabere 30 minut. Váš názor a zkušenosti jsou pro nás důležité!

Milada Kadlecová
December 1, 2016

UTIA Presentation at EMC2 Summit 2016

EMC² Summit 2016 took place 11th April 2016 at CPS Week 2016 in Vienna, Austria. We have presented this paper: Asymmetric Multiprocessing on industrial ZYNQ board with HDMI I/O.

Milada Kadlecova
May 2, 2016

EMC2 stand at HiPEAC 2016

HiPEAC 2016 conference took place in Prague, from 18 to 20 January 2016. Our team presented Xilinx SDSoC for acceleration of real-time Video Processing on custom ZYNQ modules at the 2nd EMC2 workshop and EMC2 Sundance booth.

Milada Kadlecova
January 29, 2016

Evaluation of Asymmetric Multiprocessing for Zynq System-on-Modules TE0720-02-2IF, TE0720-02-1CF, TE0720-02-1QFwith Carrier Board TE0701-05

The ARM Cortex A9 processor works together with the MicroBlaze processor, sharing the terminal and block ram. Both processors execute program from the same external DDR3 memory. The MicroBlaze processor is controlling 4 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable data path, controlled by the PicoBlaze6 controller. Download the application note and the evaluation package.

Milada Kadlecova
December 30, 2015

Invited Presentation at HiPEAC 2016 Conference

Our group will be presenting Xilinx SDSoC for acceleration of real-time Video Processing on EMC2 Development Platform, using Zynq SoC System-on-Modules at HiPEAC 2016 conference held in Prague 18 – 20 January 2016 at the Second EMC2 workshop Mixed Criticality Applications and Implementation Approaches.

Milada Kadlecova
December 30, 2015

Presentation at SAMOS 2015 conference

SAMOS XV conference was held in Agios Konstantinos, Samos Island, Greece 20 – 23 July 2015. We have presented paper Video Chain Demonstrator on Xilinx Kintex7 FPGA with EdkDSP Floating Point Accelerators. Slides.

Milada Kadlecova
August 27, 2015