Our group focuses on research, development and implementation of advanced digital signal processing algorithms, mainly in the fields of adaptive control and audio processing. We build on our experience with statistics, namely with the Bayesian approach to system identification and modeling, as well as the relevant fields of linear algebra.
Our target platforms are Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs). We use Matlab/Simulink to specify, model and verify algorithms that we later convert and synthesize to HW. As such specialized solutions are likely to be used in embedded systems, we also research features that result in extremely fast execution, use small amount of memory, small chip area or low power consumption. We achieve this both through designing new or modifying existing DSP algorithms, and using architectural properties such as dynamic reconfiguration of FPGAs...
We presented our paper Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain at the 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems in Karlovy Vary, Czech Republic. The paper was presented as a poster.
We presented our recent results of the project IDEAS at the DATE 2013 conference in Grenoble. At the university booth, we demonstrated the EDKDSP: REPROGRAMMABLE FLOATING POINT ACCELERATORS ON KINTEX FPGA WITH HDMI. This design serves as a SoC for investigation of current limits of memory interfaces for the video-based applications for the additional safety of low-weight electric-cars.
ARTEMIS and ENIAC projects presentation
We presented our recent results of the project IDEAS at the EW2013 conference in Nurnberg. At the AUTOMA booth, we demonstrated the EDKDSP Reprogrammable Floating Point Accelerators on KINTEX FPGA.
A special issue of the AUTOMA magazine 2013 (in English) has been offered on the booth. It contains an overview of the Czech participation in the ARTEMIS (embedded intelligence and systems) and ENIAC (nanoelectronics) Joint Undertakings. It also describes three projects with UTIA participation in detail.
UTLEON3 VHDL Sources Released
Following the publication of our book about the UTLEON3 processor at Springer we have released the sources of the processor on our web pages. The processor UTLEON3, derived from Aeroflex-Gaisler's LEON3, was developed in the Apple-CORE project and it is now released under the GPL license.
The UTLEON3 Book
Springer has published our book about the design, implementation and evaluation of the micro-threaded processor UTLEON3 that we have developed in the Apple-CORE project. The accompanying VHDL sources of the UTLEON3 processor, derived from Aeroflex-Gaisler's LEON3, will be released under GPL in December on these pages. For more details about the book see the Springer web.
We presented our paper Reducing Instruction Issue Overheads in Application-Specific Vector Processors at the 15th Euromicro Conference on Digital System Design in Cesme, Izmir, Turkey. The presented work is one of the results of the SMECY project.